varian data machines .

TELETYPE CONTROLLER

an option for the Varian Data Machines 620/f Computer System

Specifications Subject to Change Without Notice

varian data machines /a varian subsidiary © 1971

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FOREWORD

The 620/f Teletype Controller Manual defines and explains the logical, electrical, and mechanical parameters that control the interface between a 620/f anda TTY.

The six sections of the manual: ¢ Introduce the controller in relation to the system ¢« Describe its installation and interfacing * Give a detailed theory of operation - Describe testing and troubleshooting procedures for maintaining it in the field

¢ Reference all hardware with drawings, parts lists, and wire lists

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CONTENTS TABLE OF CONTENTS SECTION 1 INTRODUCTION ee System Overview............. eamneaeues ieeeecilanen iene mee denageaaes deteibokebatbin pxcnsenniansenaiicmueae 1-1 LZ Functional DESCripliony sssssseccscssssssesscesseecasesssnsseeeecs sdeide dubiuicanegueSIaSTeecens vestereNNeTeAseees ]-] je oe ec os a a ae eae esisiasiuaietsaieeodcateneienesecae 1-3 SECTION 2 INSTALLATION 2.1 Physical Description.................. riniesdsoorpanwaerensmnroneney: sideshavceoemnn, ppruminsecvcietnewen 2-1 ce AS RIRTAT, LAT PACE PINE aia ean nnespecce inna sa pterteinremcenn da ddsd AAA nbsA nme cern ndAKARe/SNAVEVennns 2-] 2.3. System Interconnection ....... shar nce tea tae eer pale ea elements 2-1 2 SAREE) ATG TACES sis cscacncorninddtdcaasstddconemennenstcdn bette cepa ged natenacccbismensen eet onsen 2-4 SECTION 3 OPERATION SECTION 4 THEORY OF OPERATION 4.1 CL | oe ee eee ree eee eee ee ere ee Cen e ssi iba uannatedeaiemindacademanmibaarite en A? Initial ConGHion sniscscicnascaniaiws ieeuseareueuuee Live RIE 4-] ee UE BEE i voceniceisoecnacaoiicsonians enoabeninconnapacinansinit elie Racu cian ricidete tee teancentees paabernadgemness 4-3 4.4 WG: QUEUE vcsccececccscce siadtuisuneemaemei Ee eee eC ES (GPUS PROS BOTISG oo aicnncceccecenernpnonnnssannneacenncyeneeseseessy ade cuaheldaceraciacetaacteieemmeans RTO E ee: BG FNS: SA DU saicncceteieecatccsccansvemnenmesnntocasescarenusansancmansennnnsinie ns ceenntenmaresnrwen 4-9 eF =—- PUNPRGIYIOVNIGS,, ..ccarecvereosdnesaxennnseresnnrdbinadonnss sacar deer tnunsteReTes piiliet occcsenh) svistebsneretics 4-16 £6 «Programming ConsideratlonSicitcstssssccanscescsccusassnsccnanenccncsssarsaunsoaviecvemmnnnenn Seed 4.9 Description of Commands.................... ssh auseace wane -tcumeesuas satin cepese teem aetaeaeee 4-22

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CONTENTS

SECTION 5

MAINTENANCE

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SECTION 6

DRAWINGS AND PARTS LISTS

APPENDIX A TELETYPEWRITER ASCII CODES

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CONTENTS LIST OF ILLUSTRATIONS 1-1 Teletype: Controller Furictions ws ceccnsscsccnsseanianiree cuneate 1-2 21. TE COMpOnent Layout ASSETTINYcccssnceccasmssvecenscemmciennanxcrerinssenienebersanrnenieaessacnens 2-2 2:2 Card Locations for TC and Clocks.............ssseacwen iPM INN 2-3 2-3. ~+Relay Isolation for TC/TTY Interface........... ‘icsciassiate ssoatanier tat ecaeoesesiiaeaiae visser 2-9 em = TTY GGARPROTED occa ssn seexenniccadinpneranccs 13.4 abd SAWS RENE EERE eso 2-10 2-5 Input Character Sampling............... sissies cdaaietantaainaenipenie aaa naire asada 2-11 2-6 Misadjusted Input Clock..............0...c cee. Ap UABRLReE RRS Re EEE pennants 2-12 4-1. TTY Functional Block Diagram..............0...cccccceecceseeeees ie eeieeaiedcntenemneed t= 2 External GOntrol | WG sss secs scseenieenyanienen i exer 4-4 AS Gutput from: the CPU Bo: Tres TC. Tie cnscccccasassscssmusnmansaerneramenenasnes jaasadeni 4-6 4-4 Data Trarster Out J ttitGevcecccmnsccnnniawmesnswnrsiemmeenws 4-/ A SeOiSO RESOONSE “TAMU Bie icccsnncrencnccmminenaxenaniciaiarmeaseneeneucammmnmnnesaane cunnsaunonesarevensns 4-10 46 (nut Start Bit VMNe sccnmemenes wacmusmnmnmianomnnn 4-11 AF Input trom He TTY 86 Bie TC Te ccccsseusscscearesvascessesiaosasensensmnensanmanenenx 4-12 4-6 Data Trarster Wi TUG esissciccesssnssecminenn amare ena 4-13 5-1 Shift Clock Pulse (RSCP +) Delay Adjustment..................... seiieneiutememiecsins 5-3 5-2 Waveforms for Receive Clock Adjustment..............0...ccccccccceeceecnecneceeceeeneeseeeneenees 9-4 5-3. RSCX+ Centering Adjustment .................. Giessen eee cdea ed npoenicOP 5-4 Waveforms for Transmit Clock Adiusinent A SiN gS ANEAAD alee aed aS NTE 5-6 LIST OF TABLES

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SECTION 1 INTRODUCTION

1 SYSTEM OVERVIEW

The Model 620/f Teletype Controller (TC) is a mainframe option for the Varian Data Machines 620/f computer system. The TC controls the command and information transfer between the computer and a factory-modified Teletype (TTY).

The TC card contains all circuitry except for the transmit/receive clocks and relays Kl] and K2 on the clock card. The TC plugs into the CPU tray, which slides into the mainframe of the computer. Each TC can control one TTY. If more are required, the additional circuit card and a special buffer card plug into an expansion chassis.

Memory access for the TC can be controlled directly by the CPU or indirectly through the 1/O bus. If a system requires more than one TTY, the additional TC is indirectly controlled. A TTY buffer board (assembly 01A0688-000) is required for TTY/TCs 2 through 8. Additional TCs are 620/i-type units; they operate with the buffer interlace controller (BIC).

The factory-modified TTY controlled by the TC can be a model 33 ASR, 35 ASR, or 35 KSR. The ASR models have automatic send and receive facilities and include a paper tape reader and punch; the KSR model uses only keyboard-entered instructions and data.

1.2 FUNCTIONAL DESCRIPTION

The TC is functionally divided into seven circuits: input and output registers, input and output timing controls, TC/CPU interface, and TC/clock card/TTY interface (see figure 1-1),

1 ee | Input Register

The input or read (R) register stores eight bits of data from the teletype. When the CPU generates an input data command, the R register places its data on the A bus.

Lz.2 Output Register

The output or write (W) register stores eight bits of data from the CPU. When the CPU generates an output data command, the W register is loaded from the bidirectional A bus.

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SECTION 1 INTRODUCTION

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VT11-0998 Figure 1-1. Teletype Controller Functions

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SECTION 1 INTRODUCTION

1.2.3 Input Timing Control

The input timing control circuit provides event storage, gating, and a 4.55-millisecond clock signal to regulate three input sequences. These sequences are: start data input, load the R register with input data from the TTY and transfer data to the CPU via the A bus.

1.2.4 Output Timing Control

The output timing control circuit provides event storage, gating, and a 9.1-millisecond clock signal to regulate two output sequences after the TC is ready to write. These sequences are: load the W register with output data from the CPU and transmit data to the TTY.

1.2.5 TC/CPU Interface

The TC/CPU interface circuit provides bidirectional A bus drivers and receivers for the respective R register and W register. This circuit also includes gating logic for control Signals to and from the CPU.

1.2.6 TC/Clock Card/TTY Interface

The TC/clock card/TTY interface circuit provides two relays to transmit and receive serial data signals, respectively, to and from the TTY. This circuit also includes transmit/receive clocks and cabling between the TTY and the clock card. Operation between the TC and TTY is full-duplex, serial, and asynchronous. Appendix A gives TTY ASCII codes.

1.3 SPECIFICATIONS

The physical, electrical, and operating specifications of the TC are listed in table 1-1.

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SECTION 1 INTRODUCTION Table 1-1. Teletype Controller Specifications Parameter Description Organization Contains input and output registers, timing control circuitry for simul- taneous two-way transmission, and CPU/TTY interface logic Peripheral Device A factory-modified TTY model 33 ASR, 35 ASR, or 35 KSR including a cable Speed TC operation is controlled by TTY speed. Ten characters per second (100 milliseconds per character) at either random or sustained rate Modes Input: from keyboard or paper tape Output: to typewriter or paper tape Device Address TC 001 (additional TCs, 002 through 007) sense Responses Ready to read Ready to write Memory Access Control By CPU directly or indirectly Types of Interrupt Write ready and read ready interrupts available to a priority interrupt module (PIM) Logic Levels Positive logic Internal True: +2.4 to +5.5V dc False: 0.0 to +0.5V dc Interrupts and True: 0.0 to +0.5V dc CPU/TC Interface False: +2.4 to +5.0V dc

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SECTION 1 INTRODUCTION

Table 1-1. Teletype Controller Specifications (continued)

Parameter

BIC Capability

Size

Interconnection

Connectors

Input Power

Operational Environment

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Description

With additional 620/i-type controllers only

Two 3-by-15-inch (7.7 x 38.1 cm) etched-circuit cards (TC and clock circuit card)

Interfaces with CPU, I/O bus, and TTY through mainframe backplane connector

One 182-terminal card-edge connector (inserts in female connector on CPU tray). TTY connects to a three- terminal connector at rear of main- frame

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SECTION 2 INSTALLATION

2.1 PHYSICAL DESCRIPTION

The TC is on a 3-by-15-inch (7.7 x 38.1 cm) etched-circuit card (DM274). This is a socket card type 2 accommodating one 24-pin, four 16-pin, and sixty-four 14-pin sockets. All components are integrated circuits (ICs). All connections to the TC are through card-edge connectors P1, P2, and P3, which have 76, 30, and 76 pins, respectively. These mate with connectors J40, J41, and J42 on the CPU tray.

The clock board assembly is a printed circuit card type 3 for discrete components with the Same dimensions and edge connector as the TC card (DM253). The edge connectors mate with connectors J34, J35, and J36 on the CPU tray (see figure 2-1).

Device address 001 is automatically wirewrapped; additional TC device addresses are handwired.

2.2 SYSTEM LAYOUT AND PLANNING

The TC circuit card is located in card slot 13 of the CPU tray. The card slots in the CPU tray, that is mounted in the mainframe, are numbered 1 through 14 from rear to front when facing the front panel. If a system includes more than one TC, the additional circuit cards are located in an expansion chassis and require special TTY buffer cards. Optional controllers and the TTY buffer are on 7.75-by-12-inch (19.7 x 30.3 cm) cards.

The clock card is located in card slot 11 on the CPU tray in the mainframe (figure 2-2).

2.3 SYSTEM INTERCONNECTION

The TC and clock circuit cards are inserted into their designated card slots when the CPU tray is extended out the front of the mainframe and held by an extender assembly bolted to the front of the mainframe. The cards are inserted into the mounting guides of slots 13 and 11 with the component side of the cards toward the backplane connectors.

Apply moderate pressure to seat the card-edge connectors firmly into the mating connectors on the CPU tray. To prevent damage to the connectors or to the nylon guides, apply even pressure across the top of the cards during insertion. The cards have ejector handles for unseating them from their mating connectors. The transmit (TTXX-T), receive (TTRX-T), and return (TTSR-T) lines extend from clock card slot 11, P3, at A30, A34, and A36, respectively, and connect to J13 at the rear of the CPU mainframe through P2 on the CPU tray. J13 mates to the TTY through a 20-foot cable.

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Figure 2-1. TC Component Layout Assembly

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SECTION 2 INSTALLATION

Figure 2-2. Card Locations for TC and Clocks

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SECTION 2 INSTALLATION

2.4 SIGNAL INTERFACES 2.4.1 General

The TC interfaces with the basic computer and a factory-modified TTY. No other options are required; however, the TC can interface with a PIM. This section describes the TTY interface in a general manner. The PIM interface and interface signal are also described. Refer to the manuals and reference material supplied with the TTY equipment for specific information.

2.4.2 Teletype Interface

The TC interfaces a model 33 or 35 TTY via the clock circuit card. The TTYs are modified at the factory prior to delivery to the customer. To modify the 33 ASR TTY:

a. Set the TTY for 20 mA operation. This includes the addition of a wire that enables the TTY to supply " battery" for the send and receive data loops to the clock card (the TTY is the current source for the TC relay drivers.

b. Set the TTY for full-duplex operation.

c. Disable the WRU contacts.

d. Disable parity on the keyboard.

e. Modify the answer-back drum.

f. Install the 180801 function lever.

The model 35 is similarly modified. Model 33 and 35 TTYs are electrically interfaced and cabled to the TC in almost the same manner, although they are physically quite different in appearance and in their internal operation.

The cable used for the TC/TTY interface for the 33 ASR runs from S connector plug P2 in the TTY to J13 at the rear of the CPU. The S connector is located at the right rear, top row, second connector from the right. The cable (drawing 53C0266) is normally 20 feet long with three leads in a cable.

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SECTION 2 INSTALLATION

The TTY end of the cable (P2) includes two other wires. Pins 7, 4, and 5 are connected. These connections tie internal TTY leads brought into the S connector plug as part of wiring. Note that both ends of the cable are keyed to ensure proper mating.

The cable between the model 35 TTY and the TC runs from J13 which connects to T1 at the rear of the CPU to a power terminal block in the TTY. This terminal block is located at the right lower rear of the cabinet behind the TTY printing mechanism.

Clock Card-Pin J13 End P2 End (-33) TB End (-35) Function P3-36 l 9 Terminal 4 Return P3-34 2 6 Terminal 5 Receive P3-30 3 8 Terminal 7 Send

NOTE

The TTY cable is normally installed at the TTY by Varian Data Machines before customer delivery.

The model 33 TTY requires about 3 amperes of ac power. The model 35 TTY requires about 6 amperes of ac power.

2.4.2.1 TTY DESIGN

The 33 ASR is primarily designed for light to medium use. Normally, it is the basic computer input/output device and is the most widely used unit. Its full-duplex operating mode allows simultaneous input and output.

The 35 ASR performs the same function as the 33 ASR, but it is designed for heavy, sustained use.

The 35 KSR is used for keyboard send/receive only and lacks the paper tape punch (PTP) and paper tape reader (PTR) capability of the ASR models. The operating characteristics are similar to model 33 keyboard operation. This unit is also designed for heavy, sustained use.

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SECTION 2 INSTALLATION

2.4.2.2 TTY INPUT METHODS

TTY input can be via the keyboard or the PTR. At the keyboard, the operator types at a random rate not greater than 10 characters per second (cps), the maximum rate for TTY input. Standard eight-level paper tapes are read by the PTR at a rate of 10 cps.

2.4.2.3 TTY OUTPUT METHODS

TTY output is either printed (typed) or punched on paper tape. For the printer or the PTP, the TC sends control codes or data at a random rate or at the maximum output rate of 10 cps. Data are printed, or control functions, such as line feed or carriage return, are performed on the printer. Similarly, control codes regulate the operation of the PTP, and data are punched into eight-level paper tape.

2.4.2.4 TTY SWITCHES

The ON/OFF switch controls the motor. The power supply and battery for TC relay drivers remain on, independent of this switch.

NOTE

If the TTY motor switch is in the ON position when the computer power switch is off, an open circuit or run command will be transmitted to the TTY. In this case, the TTY motor switch should be in the OFF position.

The line switch controls the TC/TTY interface. In the ON-LINE position, the interface is complete, and the TTY is under CPU control. In the OFF-LINE position, the TTY is independent of the TC, and can be used for printing or preparing tapes.

The following switches control the tape and are not on the 35 KSR. The START/STOP/ FREE switch on the PTR causes the tape to move in START, to stop in STOP, and to be released from the sprocket drive wheel in FREE. Pressing BSP on the PTP backspaces the tape one character. Pressing REL removes pressure from the tape. Pressing LOCK ON locks the punch on (prevents change of punch status). Pressing UNLOCK unlocks the punch and enables punch status change by the TC or from the keyboard.

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SECTION 2 INSTALLATION The 35 ASR mode switch mechanism enables the following operating modes. Position Keyboard Reader Printer Punch K On line Disabled On line Off line KT On line On line On line On line T Off line On line On line Off line TS Off line On line Disabled Off line TTR Off line Disabled Disabled On line

2.4.2.5 TTY FUNCTION CODES

The TTY receives control codes from the TC that cause it to perform specific functions. The codes are listed below. An enable code must follow a disable code. Codes R, T, Q, and $ are not applicable to the 35 KSR.

Code Bit Format Function

Control A 10000001 Enable printer Control D 10000011 Disable printer Control R 10010010 Enable punch Control T 10010100 Disable punch Control Q 10010001 Enable reader Control S$ 10010011 Disable reader

2.4.2.6 RELAY ISOLATION

Relays K1 and K2 in the TC perform the actual interface between the TC and the TTY. The relays are used to electrically and physically isolate the two units.

K1, the receiving relay, is driven by the TTY. K2, the sending relay, is driven by the TC. The relays switch approximately 20 milliamperes of current on or off the line. This method of interface is called ' make-break" . Each relay can be said to drive or be driven by a current loop. When there is current flowing through a relay coil, the relay contacts and the current loop are closed. The line is then in the make condition (also referred to as the mark condition). When no current flows through the relay coil, the relay contacts and the current loop are open. The line is then in the break condition (also referred to as the Space condition). The steady state of the loops is the mark condition when both the computer and TTY power is on, and both K1 and K2 relays are energized. When either the computer or TTY power is off, the steady state of the loops is in the break condition, and neither K1 nor K2 is energized.

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SECTION 2 INSTALLATION

Except for the difference in switching control location, the send and receive loops have identical functions. The loops are shown in full-duplex configuration in figure 2-3. The factory-modified system is full-duplex to provide simultaneous transmission of data in both directions.

The current source for the two loops originates in the TTY and is sometimes referred to as " battery" . The CPU and TC use no loop source current, since they are isolated by the K1 and K2 relay contacts. Typical current in a factory-modified TTY interface loop is 20 mA.

This relay-controlied current-loop interface method enables the CPU-TC and the TTY to be placed far apart without noise interference, ground loops, etc., affecting the system. Normally, the TTY cable is 20 feet long.

When either the TTY or the TC sends data, K1 or K2 operate (make or break) to conform to the character pattern being sent. The normal relay switching rate is 9.1 milliseconds per bit. Characters are sent or received serially by the current loop.

2.4.2.7 TTY CHARACTER BIT FORMAT

Each teletype character or command is serial and is divided into 11 periods or bits consisting of one start bit, eight data bits (the eight bit is always mark), and two stop bits (see figure 2-4).

The bit pattern for the character shown in figure 2-4 is 10101011. The bit length is 9.1 milliseconds and the bit rate is 110 bits per second (bps). The character length is 100 milliseconds, and the character rate is 10 cps. The start bit is always a space = zero bit = no current in loop = loop open. Data bits are either mark or space. A mark = one bit = current in loop = loop closed.

The eighth data bit is always mark. It might be used by the TTY as an even parity bit on

an optional basis. The stop bits in the character bracket the data bits. This simplifies the design and operation of the TC receiving circuitry.

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SECTION 2 INSTALLATION

TTY | SEND LOOP at

K2 O—pi = 20 mA bLe—C LOOP | CURRENT SOURCE oP INTTY kke—c K] ; <7 RECEIVE LOOP tomes

NOTE: Equivalent, not actual, circuit with two independent current loops for full-duplex operation. The current loops may have a single common current source and return wire. Isolation is achieved by relays.

VTI1-0561 Figure 2-3. Relay Isolation for TC/TTY Interface

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SECTION 2 INSTALLATION

NOTE

The expression, the TTY is running open, means the send loop to the TTY lacks current = steady spacing condition. This occurs if relay K2 remains open, if the loop current source fails, or if the send loop opens at any point.

2.4.2.8 TTY INPUT CHARACTER

The receiving circuitry synchronizes at start-bit time. The TC receiving oscillator (4.55- millisecond clock) normally begins to run at the leading edge of the start bit. The bit pattern is sampled and shifted in the center of the start bit and continues at the center of each data bit through to the eighth data bit. Normally, each sampled bit is shifted into a register. When the last data bit has been sampled and shifted, the character is ready for transfer to permanent storage (e.g., the computer). The TC enables transfer to the CPU at the middle of the first stop bit. The stop bit period is used for the transfer of the character to the CPU; therefore, these bits are not sampled. Typically, the TC receiving oscillator stops after the data bits and the first stop bit are transferred and will not start again until a new Start bit is received (figure 2-5).

To keep the receiving unit synchronized with the sending TTY, the receiving oscillator or

LAST STOP BIT—. END FIRST STOP BIT

EIGHT DATA BITS _

- TWO PREVIOUS STOP BITS OR NORMAL LINE STEADY STATE

VTI1-0560 Figure 2-4. Typical TTY Character

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SECTION 2 INSTALLATION

START BIT INPUT 1 2 3 4 5 6 7 8 —_— = 1} ofr} ojpyryofyrstrry, fof | i FIRST STOP BIT LAST STOP BIT SAMPLE | _ VTII-O559

Figure 2-5. Input Character Sampling

equivalent timing circuit must be allowed to stop and restart when the start bit for the next character occurs. If the sending device outputs a new start bit before the receiving oscillator has time to stop and recover, the two units are out of synchronization and erroneous data result. The next new character start bit may occur immediately after the stop bit or may not occur for an indefinite time interval. This is typical of asynchronous transmission. The receiving unit must be able to receive and synchronize to new data at any time.

2.4.2.9 TTY OUTPUT CHARACTER

The TTY is assumed ready to receive data at any time. The TC output sequence is as follows.

A character is loaded into the output register. A continuously running oscillator circuit is synchronized when ready to send a start bit. All bit times (start and data) are equal, and each bit takes one oscillator period. The oscillator and sync pulse initiate the start bit and enable the serial shifting of one character to the TTY. The last stage in the register drives the relay send circuitry (K2). The oscillator continues to run and shift out all eight data bits.

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SECTION 2 INSTALLATION

When the last data bit is sent, the TC obtains a new character from the CPU in preparation for the next character transmission. The oscillator in the TC continues to run during the stop bit. Typically, the TC obtains a new character during the last stop bit. If there are no more output characters, the TC oscillator continues running and places a Steady one-bit level on the output line. The TTY can then await a new start bit which occurs on the next output character.

2.4.2.10 ASYNCHRONOUS TRANSMISSION

The previous subsections detailed basic TTY input and output. Several points should be stressed.

a. The sending unit transmits at a full or random rate at any time.

b. The receiving unit must be able to accept data at any time, at a full or random rate.

c. The receiving unit must resynchronize with each new start bit (every character)

to maintain proper synchronization. The oscillator used for this purpose is called a Start-stop or gated synchronizable oscillator.

INPUT } , '

SAMPLE

VTI1-0558 Figure 2-6. Misadjusted Input Clock

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SECTION 2 INSTALLATION

d. The length of the output character must be carefully maintained. The receiving circuit can normally tolerate some distortion (less than 1/2 bit per total character). If the length of output characters is short or long and cannot be corrected, the receiving sampling circuitry can sometimes be adjusted to compensate. The waveforms of figure 2-6 illustrate an example of proper output character length but misadjusted input timing.

2.4.3

PIM interface

The PIM drivers are wired from the TC to the PIM logic (DM124), which is either in the |/O backplane of the mainframe or in one of the expansion chassis. The computer must be equipped with the PIM in order to use these drivers.

2.4.4

Interface Signals

The TC interfaces with the computer and the TTY via the control and data lines listed in table 2-1. A circuit-card pin number follows each signal mnemonic. For definitions of the

mnemonics, refer to section 4.

98 A 9908 160

Table 2-1. TC Inputs and Outputs

Input Signals

ABOO-C,P1-55 ABO1-C,P1-56 ABO2-C,P1-57 ABO3-C,P1-58 ABO4-C,P1-59 AB05-C,P1-60 AB06-C,P 1-61 ABO7-C,P1-62 AB08-C,P3-37 AB11-C,P3-14 AB13-C,P3-35 AB14-C,P3-36 DRYX-C,P3-18 FRYX-C,P3-20 IUAX-C,P3-17 RCLP,P3-12

SYRT-C,P3-38

Output Signals

ABOO-C,P1-55 ABO1-C,P1-56 ABO2-C,P1-57 ABO3-C,P1-58 AB04-C,P1-59 AB05-C,P1-60 ABO6-C,P1-61 ABO7-C,P1-62 |UAA-I,P3-69 |UBB-1,P3-70 RDDX + ,P3-9 SERX-C, P3-34 TTDO ,P3-75 TTRX-1,P3-23 WCKP + ,P3-26

varian data machines |

SECTION 3 OPERATION

There are no operating controls or indicators on the TC or clock circuit card. Data and control between the TC and TTY are under CPU software control.

98 A 9908 160 3.]

1) Ee Pere = Seer ae

varian data machines

SECTION 4 THEORY OF OPERATION

4.1 GENERAL

The theory of operation is described as a series of sequences that exercise the TC. Refer to section 6 for the TC logic diagram 91D0219 (DM274) and clock board circuit diagram 91C0209 (DM253). Three-digit numbers in parentheses indicate the chip location. The first number locates the sheet, the following letter and number indicate the chip location on the controller board. Circuit elements that are not on the DM274 card are followed by their circuit board number in parentheses.

Signal mnemonic levels referred to in the theory of operation are the levels of the signals at their point of origin or their entry into the TC. Stages of inversion are disregarded for the purpose of clarity. Signals resulting from the outputs of flip-flops are designated FF set and FF reset if they are high when the flip-flop is set or reset, respectively. J-K flip-flops (74H108) are negative-edge-triggered.

The write (transmit) and read (receive) shift registers each have two 7495 medium scale integrated circuit chips. During a write (DTOX+) operation, the W register is parallel- loaded because the mode control is high (+ 5V dc). During a read (RRCX-) operation, the R register is cleared by parallel-loading of high (+5V dc) and serial-loaded with mode control low (gnd). The write register is never cleared. Data are transferred to the output pins when the clocks (pins 8 and 9) go from high to low and the data are present at the inputs prior to clocking.

Figure 4-1 presents a functional block diagram of the TTY for reference when studying the descriptions of TTY theory in the following subsections.

4.2 INITIAL CONDITION

When computer power is first turned on, the TC and the CPU circuitry can be in an undefined state. Pressing the RESET switch on the control panel initializes the TC (and the computer) to properly perform various functions under program control. Basically, this enables the TC to monitor the TTY for input characters and to accept output characters from the CPU to the TTY. When initialized, the TC also transmits a steady mark to the TTY by keeping relay K2 (DM253) energized. The TC can also be initialized under program control; the command, however, must not be issued while the TC is communicating with the TTY.

98 A 9908 160 4-]

cv

O9T 8066 V 86

ABXX-C (BITS 0-7)

ABO6-C ABO/-C AB08-C ABII-C AB13-C AB14-C IUAX-C SYRT-C FRYX-C DRYX-C SERX-C IUAA-I IUBB-I

VTII-1064

_ABXX (BITS 0-7) |

WRITE REGISTER

READ REGISTER

CLOCK Ce

CONTROL _WCKP+

Figure 4-1. TTY Functional Block Diagram

TTDO- INTERFACE R SENSE STATUS AURA : : INTERRUPT | CONTROL WRITE CLOCK CONTROL WRDY+

RRDY+ | 3 | READ | RDDX+

TTRX-T TTXX-T TTSR-T

TTY

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varian data machines

SECTION 4 THEORY OF OPERATION

NOTE

An initialization command performs the same function as pressing the RESET switch.

Either SYRT-C low or TYO08+ and EXCX+ high, which produces WIREO1 low, generates INZX+ high (1M4). INZX+ high and INZX- low verify that the following flip-flops are initialized to the state shown.

Set Reset

WRDY RRDY

WOO0X RDDX

WSYNC DTOX DTIX RRCX ROQX RSCX WSEX

As a result, the 4.55-millisecond clock is off.

Note that with the exception of flip-flop WOOX, the R and W registers are not cleared initially. If TTY power is on, the TTY energizes relays K1 and K2 (DM253), and the TC receives a steady mark. The TC is then in a line-monitoring state.

4.3 TC/CPU INTERFACE The CPU commands the TC via the A bus with signals such as FRYX-C and DRYX-C. When any such command is issued, the following device address sequence occurs.

DAXX+ is high if the proper address (01) is put on the A bus and IVAX-C its high (no interrupt). DAXX + high enables the command generation gates.

The functions of the A bus signals are: ABOO-C through ABO5-C enable device address signal DAxx+ (1N4). ABO6-C enables the output ready sense response. ABO7-C enables the input ready sense response. ABO8-C and AB11-C enable the initializing sequence. AB13-C enables the input command sequence. AB14-C enables the output command sequence (figure 4-2).

4-3

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O9T 8066 V 86

FRYX+1 | | | ) , _ ee

| | DTOX+ [] _ | _ | | | DRYX+1 | | | | _———_—_$ $$ | | |

; ee WLDX- ly W10X+ : | ————————

WSCP+ | | I i | r | | |

WCMP+ | = | —_—————— ——— —— ——— ————— h— Fy

VTI1-1065 Figure 4-2. External Control Timing

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varian data machines |

SECTION 4 THEORY OF OPERATION

I'UAX-C inhibits TC selection when the CPU has an interrupt, direct memory access (DMA), trap-in, or trap-out. The CPU can issue any of several commands. All of the following commands are accompanied by the device address, and some are also accompanied by FRYX-C and DRYX-C. The input and output timing diagrams (sections 4.4.1 and 4.6.2) illustrate the sequence that results with FRYX-C and DRYX-C.

a. Sense write ready (ABO6-C) -- FRYX only

b. Sense read ready (ABO7-C) -- FRYX only

c. Execute (initialize) (ABO8-C and AB11-C) -- FRYX only

d. Output (load/write register) (AB14-C) -- FRYX and DRYX e. Input (read/read register) (AB13-C) -- FRYX and DRYX

If a sense condition is met, SERX-C goes low. A sense command is normally issued before input or output. SERX-C low is enabled by FF set signal RRDY+ high (3U5) or FF set Signal WRDY + high (2S4). These two signals signify that the TC has an input character or is in a condition to accept an output character, respectively.

When initialized, flip-flop WRDY+ is set to enable immediate output under CPU control. Flip-flop RRDY + is not set until the TTY has loaded a complete character into the R register.

When the CPU issues an output command, a FRYX/DRYX sequence sets and resets flip- flop DTOX +. When the CPU issues an input command, a FRYX/DRYX sequence sets and resets flip-flop DIIX +.

4.4 TC OUTPUT (WRITE)

The TC output circuits include portions of the TC/CPU interface, output timing control, output register, and portions of the TC/TTY interface. Circuit elements are control flip- flops, a group of gates enabled by the A bus, a 110-Hz free-running clock that Is asynchronous to the CPU, an 11-bit write register, and an output relay to the TTY with associated drive circuitry. The data and control output waveforms illustrate the loading of output from the CPU to the TTY (figures 4-3 and 4-4). For these waveforms, assume that the TC has been initialized; the CPU has sensed write ready and issued an output command; and the output character is 01010101.

98 A 9908 160 4.5

varian data machines

SECTION 4 THEORY OF OPERATION

A BUS SIGNAL f paxx L——J bata L____ ERYX SF EL DRYX 2 a i Sn e DTOX oa eames Sesame WRDY pg, WSEX solicecemcall Mace sapeirenmenacncgnainaocesematamsoone 9.1 MS CLOCK le —— WSCP ee WLDX a 55 eee WO09X , WIOX ——_ ~~~ WO00X . _ WO01X WCSX | VUJ:.MMJSJM;M’blcié=;Jé¢#ééMtbhg ABOUT 4 uSEC ——— *The W register (W0O1X-WO08X) accepts the A bus bit pattern at WLDX time. VIil-0999

Figure 4-3. Output from the CPU to the TC Timing

4.6 98 A 9908 160

varian data machines

SECTION 4 THEORY OF OPERATION

WRDY | IG

9.1-MSEC_ | - CLOCK : WSYNC 1 Gs | wscp EL 1 | [ | | [| [| | [{ | |START WO00X Yj, *

| | K2 RELAY fore CL OF cl OP €t OP Cl OP c€L CL

BIT PATTERN START 1 Oo 1 0 1 © 1. @ STOP STOP

|. ey

*WRDY enables sense response logic. The computer can then respond at any time. The output sequence restarts as above, except actual line output of new character does not begin until. the 9. ]1-msec clock recovers. WSYNC keeps relay K2 energized after WOOX is reset and until the

9.1=-msec clock restarts.

VTI1-1000 Figure 4-4. Data Transfer Out Timing

98 A 9908 160 4-7

Ga) varian data machines ———— .

SECTION 4 THEORY OF OPERATION

Data are output from the CPU in a two-word format; the first word contains the device address and the function type, and the second word, character data. The device address is sampled on the trailing edge of FRYX-C, and data are sampled on the trailing edge of DRYX-C.

4.4.1 Load Output Register

DAxx + and FRYX +1 clock the DTOX + flip-flop true if JOTOX + is high. DTOX + is reset on the trailing edge of DRYX-C. The clocking signal (FDRY+) for both DTIX+ and DTOX + implements:

FDRY+ = (DRYX+1)(DTIO+) + (DAxx+ )(FRYX + 1)

In addition, FDORY + clocks eight bits of data into the parallel in-serial out shift register (4S3,T3) if DTOX+ is high. FDRY+ is ANDed with DTOX+ (2S5) to clear the WRDY + flip-flop (284) and preset bits W10X + and W09X+ of the write shift register (412). Note that W10X + and WO9X + are the two stop bits for the TTY character, and bit WOOX + is the start bit. The clearing of the WRDY + flip-flop enables the set input of the write sync (WSYNC) flip-flop, which results in a sync pulse on the next WOSX- clock (2U3).

The basic write clock (WCKP + ) is input to the WOSX + one-shot (2U3) to generate an 80- nanosecond pulse for clocking the write data register. On the first positive-going edge of WCKP + (after the WRDY + flip-flop is set), WSYNC (2X4) is set. The WOSX pulse that clocks WSYNC + high does not clock the data register, but is inhibited by WSEX + (2S4). The WSYNC + flip-flop resets when WCKP + goes low. WSYNC + true presets the WSEX + flip-flop and clears WOOX + to start the character transfer.

4.4.2 Output to TTY

With the WSEX + flip-flop set, subsequent WOSX + pulses clock the write register. This continues until